1. Field of the Invention
The present disclosure relates to a gate, and more particularly, to a gate drive circuit for a display device. Although the present disclosure is suitable for a wide scope of applications, it is particularly suitable for maintaining output states of scan pulses identically by minimizing load deviation between connecting units.
2. Discussion of the Related Art
Generally, a gate drive circuit generates scan pulses using a plurality of clock pulses differing from each other in phase. The gate drive circuit includes a plurality of clock transmission lines for carrying clock pulses and a shift register generating to output scan pulses using the clock pulses from the clock transmission lines.
Each of the clock transmission lines is connected to the shift register via a connecting unit. Since a distance between the shift register and each of the clock transmission lines varies, a length between the connecting units varies as well. This generates a load difference between the connecting units. The load difference causes an inter-clock pulse ascending time deviation and an inter-clock pulse descending time deviation between the clock pulses outputted from the corresponding clock transmission lines, respectively. Therefore, an ascending time deviation and a descending time deviation increase between scan pulses outputted based on the clock pulses.
However, as the scan pulses drive gate lines of a display device, if the deviation between the scan pulses increases, it is unable to avoid the degradation of image quality.